1. Field of the Invention
The present invention generally relates to analyzing packetized information and, more specifically, to analyzing packetized information spanning many clock cycles.
2. Description of the Related Art
Logic Analyzers are test and measurement instruments used, for example, to monitor bus traffic to facilitate development and testing of microprocessor systems. Logic analyzers allow inspection of patterns (i.e., particular arrangements of logic states) in logic signals, and may be configured to detect the occurrence of selected events.
Many modern communication buses (e.g., 3GIO, Hypertransport and the like) use a packet-based protocol in which each byte or word of a packet is conveyed over the bus in response to the occurrence of a clock signal. A packet may include only a few bytes, or may include thousands of bytes of data that may span many clock cycles.
Capturing desired data frequently hinges on being able to specify a sufficiently meaningful trigger condition. The desired trigger condition may comprise a simple or complex sequence of events. For example, when a person uses a logic analyzer to trace a serial bus, a trigger event may need to be established by looking at numerous bytes in a packet spanning multiple clock cycles.
Trigger events are identified by using word recognizers in conjunction with a trigger state machine. A trigger state machine is circuitry that looks at the results of the trigger resources (word recognizers and the like) and determines what action to take, such as trigger the logic analyzer, go to another trigger state and start looking for a different word among other actions. Typically, a trigger machine in a logic analyzer is used to determine when to trigger, as well as to determine what data to store.
Word recognizers are utilized to compare the incoming bytes to a predefined value or word. The incoming data is sent to the word recognizer at each clock cycle. However, since all of the information in a packet is not available within a single clock cycle, it takes most, if not all, of the word recognizers, and most of the trigger states, to define just a simple trigger event. Since the trigger machine has used most, if not all of its resources (word recognizers, trigger states, and the like) just to track an incoming packet, the trigger machine cannot perform other (additional) tasks such as, for example, “wait for packet A to occur and then trigger when packet B occurs”.
The model NT4220A packet analysis probe for PCI Express, manufactured by Agilent Technologies Inc. of Palo Alto, Calif., identifies a start-of-packet, and then looks for matches to fields within the packet header and data payload of up to the first twenty four contiguous bytes. All of the initial contiguous (e.g., twenty four) bytes are compared at one time to a reference value. While useful, this solution is relatively inflexible because it only allows a user to compare the first 24 bytes. For example, if the header of the packet is large (e.g., about 24 bytes), this solution may not be able to perform desired compare matches in the data payload or tail of the packet, or portions thereof.